Semiconductor memory device having self-aligned wiring conductor

ABSTRACT

According to the present invention, an overlay margin is secured for matching a wiring electrode  11  with a storage electrode  15  of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode  11  of titanium nitride in the active region of a semiconductor substrate or over the gate electrode, reducing the size of the opening for passing the storage electrode  15  of the capacitor of a stacked structure, and decreasing the line width of a wiring electrode  13 . By the common use of the above-mentioned plug electrodes in a CMISFET region in the peripheral circuit and in a memory cell of a static RAM, their circuit layouts can be made compact.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor memory device,such as a dynamic random access memory having a capacitor of athree-dimensional structure suitable for high density device integrationor to a static random access memory, and also to an embedded memorysystem LSI using those memory elements as cores.

BACKGROUND ART

[0002] For example, the dynamic random access memory (hereafter referredto as a dynamic RAM) has as an elemental memory unit a memory cellhaving connected thereto a capacitor to store electric charge as one bitof information and a switch transistor to write or read information intoor from the capacitor. As it forms one memory cell by the small numberof component elements as described above, the dynamic RAM is widely usedin the main memory of computer equipment that requires a large capacity.

[0003] To increase the memory capacity of the dynamic RAM, it isnecessary to miniaturize the memory cell area to increase the density ofthe memory cells.

[0004] However, in such a process, by the reduction of the memory cellarea, the effective area of the charge-storage capacitor of the memorycell is decreased and the storage capacitance decreases. Therefore, theso-called soft-error phenomenon has manifested itself that informationin the memory cell is reversed by a decrease of S/N ratio or byalpha-ray exposure, and has become a serious problem of reliability.

[0005] For this reason, there have been devised several memory cellstructures that provide a large storage capacitance without increasingthe area occupied by the memory cell. One of them is a memory cellhaving a stacked capacitor formed as a three-dimensional capacitor thatuses the vertical material faces of the storage capacitance electrode asin the crown-shaped capacitor. Memory cells of this kind are describedin JP-A-62-48062 and JP-A-62-128168, for example.

[0006] The memory cell of a 1-gigabit dynamic RAM is discussed in IEEEInt., Electron Devices Meeting, Technical Digest, pp.927-929 December(1994).

[0007] The dynamic RAM that the present inventors have conceived basedon the memory cell structure disclosed in the above-mentioned literatureis shown in FIG. 45. The structure and problem of this dynamic RAM willbe described with reference to FIG. 45.

[0008] In FIG. 45, a transistor as a switch for the memory cell(hereafter a MISFET, which is in most general use, is used) includes agate insulator 403, a gate electrode 404 and highly-doped n-typeimpurity regions 407, 408 as the source or the drain. In thehighly-doped n-type impurity regions 407, 408, there arepolycrystalline-silicon plugs 410 that pierce through a silicon dioxidefilm 409. There is an opening through a insulating film 412 on thepolysilicon plug 410. Through this polysilicon plug, a data line (wiringelectrode 413) formed on the insulating film 412 is electricallyconnected to the highly-doped n-type impurity region 407. In a spacebetween the data line (wiring electrode 413) and a word lines (gateelectrodes 404), there is formed a common opening, which runs throughthe insulating film 412 on the polysilicon plug 410 in the highly-dopedn-type impurity region 408 and a silicon dioxide film 414 on theinsulating film 412. Through this opening and the polysilicon plug 410,a storage electrode 415 of a crown-shaped capacitor formed of theabove-mentioned polysilicon is electrically connected to thehighly-doped n-type impurity region 408.

[0009] A capacitor dielectric film 416 is deposited on the storageelectrode 415, and a plate electrode 417 is provided on the capacitordielectric film 416. An aluminum wiring 419, formed on the silicondioxide film 418 on the memory cell, is used as the cell selection wireor the main word line.

[0010] However, in a memory cell that has a capacitor above the dataline as mentioned above, particularly, in the same memory cell when itis used for high device integration, the connection point of the dataline (wiring electrode 413) and that of the capacitor electrode 415 areinevitably arranged very close to each other. Therefore, it becomesdifficult to secure sufficient electrical insulation between the dataline and the capacitor electrode due to mask misalignment duringmanufacture or a shift in dimensions (side etching) in dry etching informing the opening of the insulating film 414. There is anotherproblem. In matching of the data line to the opening of the insulatingfilm 412, it becomes difficult to secure a sufficient allowance of thedata line to overlie the opening. Owing to mask misalignment or adimensional shift (side etching) in the dry etching of the wiringelectrode 413 as the data line, there os a possibility that thepolysilicon plug 410 is exposed from the above-mentioned opening andetched deeper.

[0011] Further, it has been necessary to arrange peripheral circuits,such as sense amplifiers, which are directly connected to the memorycell array, at the same pitch as the memory cells or at a twice largerpitch. In a memory for high device integration, which has a small area,it has been necessary to reduce the area occupied by the directperipheral circuits, such as the sense amplifiers. Also in the indirectperipheral circuit, there are the same problems as with the memory cellas mentioned above in reducing the area occupied by the MISFET as acomponent part of the indirect peripheral circuit and in improving thewiring density.

[0012] Further, because a three-dimensional capacitor with aconsiderable height is used for the memory cell, if such a heightdifference between the memory cell portion and the indirect peripheralcircuit portion is smoothed out, a problem has arisen that the depth ofthe contact holes in the indirect peripheral circuit portion increasesand disconnection occurs in the indirect peripheral circuit.

[0013] To solve this problem, it is effective to use polysilicon plugsthe same as used for the memory cells also for the contact areas of theindirect peripheral circuit. Doped polysilicon has conventionally beenused to form polysilicon plugs, and therefore polysilicon plugs of dopedpolysilicon could be used for memory cells comprising transistors of oneconductivity type.

[0014] However, in the indirect peripheral circuit where transistors ofdifferent conductivity types are generally used, polysilicon plugs ofdoped polysilicon of one conductivity type could not be used andtherefore it has been difficult to reduce the areas of the indirectperipheral circuits.

[0015] On the other hand, as a plug material such as mentioned above,tungsten is well known which is deposited by chemical vapour deposition(CVD). In this case, tungsten can be used for the indirect peripheralcircuit because tungsten serves as the diffusion barrier againstimpurities, but a problem has presented itself that tungsten has a lowheat resistance and reacts with silicon during heat treatment at 600° C.or higher.

[0016] Also in a static random access memory (hereafter referred tosimply as a static RAM) cell made of transistors of oppositeconductivity types formed on the principal surface of the siliconsubstrate, the memory cell area could be reduced by local interconnecttechnology. But, with technologies of this kind, it has not becomepossible to install the wiring layers of the indirect peripheralcircuit.

[0017] Further, in an embedded memory system LSI (semiconductorintegrated circuit system) using high-density dynamic, it is essentialto use as many parts common to the memory cell and logic regions aspossible.

DISCLOSURE OF THE INVENTION

[0018] An object of the present invention is to provide a semiconductormemory device, which includes a memory cell and indirect peripheralcircuit and which has high component integration and high reliability.

[0019] Another object of the present invention is to provide asemiconductor memory device, which includes a memory cell andcomplementary transistors that form a sense amplifier or a logiccircuit, and which has high component integration and high reliability.

[0020] Yet another object of the present invention is to provide adynamic RAM having stacked capacitors in high density and with increasedstorage capacity.

[0021] A still further object of the present invention is to provide adynamic RAM with a reduced memory cell area.

[0022] The present invention has been made to provide a semiconductormemory device which enables cost reduction by simplifying themanufacturing process.

[0023] According to the present invention, a semiconductor memory devicehaving a memory cell and its indirect peripheral circuit, comprising:

[0024] transistors provided on a principal surface of a semiconductorsurface;

[0025] a first insulating film provided on the transistors;

[0026] a plurality of first conductors (plug electrodes) passing throughthe first insulating film and being made of titanium nitride havingsuperior covering properties; and

[0027] a first wiring provided on the principal surface of the firstinsulating film,

[0028] wherein the first wiring is connected to the transistors by thefirst conductors.

[0029] According to the present invention, in a memory cell region, acapacitor and a transistor formed on a principal surface of a secondinsulating film on the first insulating film are connected by the secondconductor that pass through the first conductor and the secondinsulating film.

[0030] According to the present invention, the second conductor isformed so that its cylindrical portion is smaller than the diameter ofthe cylindrical portion of the first conductor.

[0031] Further according to the present invention, the first wiring isformed so that its line width is thinner than the diameter of thecylindrical portion of the first conductor.

[0032] Still further according to the present invention, a n-channeltransistor and a p-channel transistor, which constitute a complementarytransistor, are electrically connected by the first conductor.

[0033] According to the present invention, the first conductor made oftitanium nitride effectively functions as the etching stopper to dryetching of the first wiring by using a suitable material for the firstwiring and thus effectively utilizing a difference in etching ratebetween the first conductor and the first wiring.

[0034] Therefore, even if the first wiring connected to the firstconductor is arranged in such a way that the first wiring does notcompletely cover the first conductor exposed at the principal surface ofthe first insulating film, the first conductor is prevented from beingetched deeper when the first wiring is dry etched.

[0035] Because the diameter of the cylindrical portion of the secondconductor and the line width of the first wiring are both thin, acontact does not occur between the second conductor and the firstwiring.

[0036] Therefore, even if the area for the memory cell is reduced, ashort-circuit never occurs between the capacitor and the data line, andbecause the capacitor is located above the data line, the required areafor the capacitor in the memory cell can be increased to a maximum.

[0037] Further, because the titanium nitride serves as the barrier todiffusion of impurities, the first conductor is used to connect then-channel transistor and the p-channel transistor in indirect peripheralcircuit devices or in a static RAM cell formed by complementarytransistors, so that the required areas for the indirect peripheralcircuit and a memory cell can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

[0038]FIG. 1 is a sectional view of a semiconductor memory deviceaccording to a first embodiment of the present invention;

[0039]FIG. 2 is a plan view of the semiconductor memory device accordingto the first embodiment of the present invention;

[0040]FIG. 3 is an equivalent circuit diagram of the semiconductormemory device according to the first embodiment of the presentinvention;

[0041] FIGS. 4 to 10 are sectional views for explaining themanufacturing process of the semiconductor memory device according tothe first embodiment of the present invention;

[0042]FIG. 11 is a sectional view of the semiconductor memory deviceaccording to a second embodiment of the present invention;

[0043]FIG. 12 is a sectional view of the semiconductor memory deviceaccording to the second embodiment of the present invention;

[0044]FIG. 13 is a sectional view of the semiconductor memory deviceaccording to a third embodiment of the present invention;

[0045] FIGS. 14 to 17 are sectional views for explaining themanufacturing process of the semiconductor memory device according tothe third embodiment of the present invention;

[0046]FIG. 18 is a sectional view of the semiconductor memory deviceaccording to a fourth embodiment of the present invention;

[0047] FIGS. 19 to 24 are sectional views for explaining themanufacturing process of the semiconductor memory device according tothe fourth embodiment of the present invention;

[0048]FIG. 25 is a sectional view of the semiconductor memory deviceaccording to a fifth embodiment of the present invention;

[0049] FIGS. 26 to 31 are sectional views for explaining themanufacturing process of the semiconductor memory device according tothe fifth embodiment of the present invention;

[0050]FIG. 32 is an equivalent circuit diagram of the semiconductormemory device according to a sixth embodiment of the present invention;

[0051]FIG. 33 is a plan view of the semiconductor memory deviceaccording to the sixth embodiment of the present invention;

[0052]FIG. 34 is a plan view of the semiconductor memory deviceaccording to the sixth embodiment of the present invention;

[0053]FIG. 35 is a sectional view of the semiconductor memory deviceaccording to the sixth embodiment of the present invention;

[0054]FIG. 36 is a plan view of the semiconductor memory deviceaccording to a seventh embodiment of the present invention;

[0055]FIG. 37 is a plan view of the semiconductor memory deviceaccording to the seventh embodiment of the present invention;

[0056]FIG. 38 is a sectional view of the semiconductor memory deviceaccording to the seventh embodiment of the present invention;

[0057]FIG. 39 is a plan view of the semiconductor memory deviceaccording to an eighth embodiment of the present invention;

[0058]FIG. 40 is a sectional view of the semiconductor memory deviceaccording to the eighth embodiment of the present invention;

[0059]FIG. 41 is a plan view of the semiconductor memory deviceaccording to a ninth embodiment of the present invention;

[0060]FIG. 42 is a plan view of the semiconductor memory deviceaccording to the ninth embodiment of the present invention;

[0061]FIG. 43 is a sectional view of the semiconductor memory devicebased on the idea of the present invention prior to the presentinvention;

[0062]FIG. 44 is a sectional view of the semiconductor memory deviceaccording to the first embodiment of the present invention; and

[0063]FIG. 45 is a sectional view of the semiconductor memory deviceaccording to the first embodiment of the present invention.

BEST MODE OF CARRYING OUT THE INVENTION

[0064] The present invention will be described in detail with referenceto preferred embodiments.

[0065] <Embodiment 1>

[0066] Referring to FIGS. 1 to 10, description will be made of anembodiment of a dynamic RAM according to the present invention. FIG. 1shows a sectional view of the memory cell and a sectional view of theMISFET portion of the indirect peripheral circuit depicted together thesame drawing. FIG. 2 is a plan view of the memory cell. The sectionalview of the memory cell portion in FIG. 1 corresponds to a part of thecross section taken along the line X-X′ in FIG. 2.

[0067] In FIG. 1, a MISFET in the memory cell consists of a gateinsulating film 3, a gate electrode 4, and highly-doped n-type impurityregions 7, 8 as the source and drain. A MISFET in the indirectperipheral circuit consists of a gate insulating film 3, highly-dopedp-type impurity regions 9 as the source and drain. Generally, acomplementary MISFET (a CMISFET or more specifically a CMOSFET) is usedin the indirect peripheral circuit. In the present invention, too,description presupposes the use of n-channel and p-channel transistorsas the indirect peripheral circuit elements. However, description islimited to the p-channel transistor.

[0068] Plug electrodes 11 made of titanium nitride are used both in thehighly-doped n-type impurity regions 7, 8 and in the highly-doped p-typeimpurity regions 9. The plug electrode on the highly-doped n-typeimpurity region 7 of the memory cell is connected to a wiring electrode13 as the data line. A storage electrode (bottom electrode) 15 of acrown-shaped capacitor is provided above the data line 13. The storageelectrode 15 is connected to the plug electrode 11 on the highly-dopedn-type impurity region 8, and is electrically connected to the MISFET.In the silicon dioxide film 14 as the inter-layer dielectric, there isformed an opening that is smaller than in diameter than the plugelectrode 11, and the storage electrode 15 is connected to the plugelectrode 11 through this opening. A capacitor dielectric film 16 isdeposited on the storage electrode 15, and a plate electrode 17 of thecapacitor is provided on top of the capacitor dielectric film 16, thusforming the crown-shaped capacitor.

[0069] On the other hand, the plug electrodes 11 are formed on thehighly-doped p-type impurity regions 9 as the source and drain of theMISFET and also on the gate electrode 4. As shown in FIG. 1, common plugelectrodes 11 can be provided similarly for the gate electrode 4 and thehighly-doped p-type impurity region 9. As mentioned earlier, the MISFETmay be of the n-channel type or of the p-channel type, and the gateelectrode may be of n-type or p-type conductivity. Moreover, the wiringelectrode 13 may be connected to the plug electrodes of the indirectperipheral circuit to use as wiring of the indirect peripheral circuit.

[0070] Referring to the plan view of the memory cell in FIG. 2, theplanar positional relationship of the MISFET and the capacitor in thememory cell will be described. In FIG. 2, the word line 21 is formed bya common gate electrode 4 (FIG. 1) of the MISFETs, and the data line 23is formed by the wiring electrode 13 (FIG. 1). The word lines are laidin the Y-direction and the data lines are laid in the X-direction, andthe crown-shaped capacitors 25 (storage electrodes 15) are formed abovethe word lines and the data lines. The capacitor 25 is connected throughan opening 24 to the plug electrode 11 in the active region (T-region)in the space between the word line and the data line. It is notnecessary to provide the data line 23 with an overlay margin withrespect to the opening 22. Therefore, the data line 23 is made in aso-called dog-bone free structure as shown in FIG. 2.

[0071] The above-mentioned dog-bone free structure can be applied inexactly the same way to the indirect peripheral circuit. For example,FIG. 3 shows a latch-type sense amplifier, but the present invention asshown in FIG. 1 can be effectively applied to a flip-flop circuit, suchas is formed by having a pair of CMISFETs as inverters in the senseamplifier arranged (Lin cross connection. The above-mentioned senseamplifier in FIG. 1 shows the repetition unit, and the data pair linesconnected to the adjacent memory cell are divided into data pair linesD1 and D1B and data pair lines D2 and D2B. A data-pair-line select lineISO1 or ISO2 separates the lines of each pair. The above-mentionedflip-flop circuit is connected to the data pair lines, and a signalsensed by the data line is amplified by driving the common source lineSNL to ground potential and SPL to the power supply voltage. Switchtransistors connected to the I/O signal lines are further connected tothe data pair lines, and a row select line YL controls input and outputof a signal.

[0072] The first embodiment of the present invention will be describedin greater detail by referring to the sectional views of themanufacturing process in FIGS. 4 to 10. FIGS. 4 to 10 show the memorycell region and the indirect peripheral circuit region depicted togetherin the same drawing as in FIG. 1.

[0073] As shown in FIG. 4, an isolation (field oxide film) 2 isselectively formed in a silicon substrate 1 having a crystal plane (100)by a well-known technique. In the active regions demarcated by theisolation 2, MISFETs, each having a gate electrode 4 and highly-dopedn-type impurity regions 7, 8 or highly-doped p-type impurity regions 9,are formed by well-known methods. The gate of the MISFETs is 0.2 μm inlength. In the formation of the isolation, various method may be used,such as a selective oxidation method (LOCOS) or trench isolation thathas a silicon dioxide film entrenched in a shallow groove of a siliconsubstrate. In this case, n-channel MISFETs are used, but p-channel typesmay be used. Furthermore, a LDD (Lightly Doped Drain) structure may beused to reduce the device deterioration by hot carriers. To useself-aligned contact to the gate in order to avoid a formation of gateto contact short circuit by dry etching, silicon nitride films 5, 6 areprovided at the top or to the sidewalls of the gate electrode 4 by awell-known method as shown in FIG. 4.

[0074] Subsequently, as shown in FIG. 5, a silicon dioxide film 10containing boron and phosphorus is deposited by a well-known CVD method,and the surface of the silicon dioxide film 10 is smoothened byannealing at a temperature of about 800° C. The silicon dioxide film maybe flattened by a method such as a well-known CMP (Chemical MechanicalPolishing). Then, openings 39, 40 about 0.2 μm in diameter are formed inthe silicon dioxide film 10 by photolithography and dry etching of thesilicon dioxide film. In this step, photolithography using excimer laseris carried out. In dry etching, it is preferable to form a siliconnitride film serving as the etching stopper at the lower portion of thesilicon dioxide film 10 and form the openings by self-alignment to theisolation region. Preferably, the opening 40 that includes the portionwhere there is the gate electrode should be formed by photolithographyand dry etching, which are performed separately from the similarprocesses mentioned above. Note that when the etching stopper mentionedabove is used, dry etching should be carried out both on the silicondioxide film and the silicon nitride film.

[0075] After this, as shown in FIG. 6, a titanium nitride (TiN) film isdeposited to a thickness of about 300 nm by a well-known CVD technique,and the titanium nitride is etched back by anisotropic dry etching, andplug electrodes (titanium nitride: TiN) 11 are formed in theabove-mentioned openings 39, 40. In this case, it is possible tosimultaneously flatten the surface and form plug electrodes by polishingthe titanium nitride film and the silicon dioxide film 10. Besidestitanium nitride, a heat-resistant barrier material, such astitanium-tungsten (W) may be used.

[0076] Subsequently, as shown in FIG. 7, a silicon nitride film 12 witha thickness of about 50 nm is deposited by a LPCV process, openings 22(FIG. 2) are formed by photolithography and dry etching, tungsten isdeposited to a thickness of about 100 nm as the wiring electrodes 13 andthe deposited tungsten is patterned by photolithography and dry etching.Incidentally, as a material for the wiring electrodes 13, a highrefractory metal other than tungsten or, for example, a composite filmof a silicide film, which is a high refractory metal, and a polysiliconfilm can be used.

[0077] After this, as shown in FIG. 8, a silicon dioxide film 14 with athickness of about 0.5 to 1 μm is deposited at a temperature of about400° C. by a well-known CVD process using TEOS(tetra-ethyl-ortho-silicate) gas, and the surface is flattened by awell-known CMP method. Subsequently, openings 25 are formed in thesilicon dioxide film 14 and the silicon nitride film 12. The diameter ofthe openings is about 0.1 μm.

[0078] As shown in FIG. 9, a first polysilicon film highly doped withn-type impurities is deposited (not shown) to a thickness of about 100nm by a well-known LPCVD method. In this case, this polysilicon film isembedded in the openings 25. Though not shown, a silicon dioxide filmwith a thickness of about 500 nm is deposited and is patterned byphotolithography and dry etching to form the storage electrodes. Afterthis, a second polysilicon film is deposited with better step coverageby LPCVD, and by etching the first and second polysilicon films byanisotropic dry etching and removing the silicon dioxide film about 500nm thick mentioned above, crown-shaped storage electrodes 15 are formed.Note that before removing the silicon dioxide film mentioned above, itis desirable to have a silicon nitride film provided at a bottom layerof the silicon dioxide film.

[0079] After this, as shown in FIG. 10, a capacitor dielectric film 16,such as tantalum pentoxide (Ta₂O₅) film is deposited, which has agreater dielectric constant than the silicon dioxide film. In this case,a CVD process for better step coverage is used as a deposition method.The effective oxide thickness of the capacitor dielectric film shouldpreferably be 3 nm or less for a large-capacity dynamic RAM of1-giga-bit class. Incidentally, here the polysilicon film is used forthe storage electrodes 15, but a high refractory metal film, such astungsten or titanium nitride, may be used. In this case, the effects ofthe natural oxide on the surface of the polysilicon film can be avoided,and the effective oxide thickness of the capacitor dielectric film canbe decreased. As the material for the capacitor dielectric film, it ispossible to use well-known high ∈ dielectrics such as a SrTiO₃ film anda (Ba, Sr) TiO₃ film (BST film) or a ferro-electric film in addition toa composite film of silicon nitride and a silicon dioxide film. Afterthis, a high refractory metal film, such as tungsten or titaniumnitride, is deposited to a thickness as large as 300 nm and is processedby photolithography and dry etching to form a capacitor plate electrode17 (top electrode). As the method for depositing a material for theplate electrode, a CVD method for better step coverage should preferablybe used.

[0080] Next, as the inter-layer insulating film, a silicon dioxide film18 about 200 nm thick is deposited, openings are formed in the silicondioxide films 14, 18 above the metal wiring 13, and after this, a metalwiring 19 is formed, thus completing a semiconductor device according tothe present invention. A low resistivity metal such as aluminum ispreferred for the metal wiring 19, and and may be used for wiring insideof a memory array as shown in FIG. 1. Further, a well-known plugtechnology or CMP method may be used to flatten the inter-layerdielectric when forming the metal wiring 21.

[0081] It ought to be noted that a greater storage capacity can beobtained by making undulated the surface area of the polysilicon storageelectrode 15 in the first embodiment to increase its surface area. Inthe first embodiment, titanium nitride is used for the plug electrodes,but titanium-tungsten (TiW) may be used, or another material that isslower in etching rate in dry etching of the wiring electrode 13 andthat serves as a barrier to impurity diffusion may be used.

[0082] Further, as shown in FIG. 44, if titanium (Ti) 146 is provided atthe underside of the plug electrodes 11 and titanium silicide (TiSi₂)147 is formed at the interface the titanium and the silicon substrate,it is possible to prevent an increase in contact resistance with thehighly-doped impurity regions 7, 8 and 9.

[0083] Further, as shown in FIG. 45, polysilicon plugs 248 may be placedon the highly-doped impurity regions 8 at the storage nodes at which thecapacitors are connected. In this case, because the titanium nitride ortitanium silicide does not directly contact the highly-doped impurityregions at the storage nodes, the junction leakage current can bereduced.

[0084] According to the first embodiment, because the plug electrodes11, which connect the data lines to the highly-doped n-type impurityregions of titanium nitride, are made of titanium nitride, even if theplug electrode lying underneath the data line is exposed during etchingthe data line material, the plug electrode is not etched, so that theoverlay margin for openings for connection between datalines can bereduced.

[0085] Further, the storage electrode of the capacitor is not directlyconnected to the silicon substrate but connected through theintermediary of the plug electrode, a smaller amount of etching isrequired in dry etching when forming the openings for connection to thestorage electrodes, and the swell at the openings due to side etchingresulting from dry etching can be decreased. Consequently, the shortmargin between the storage electrode and the data line increases. At theplug electrode connected to the storage electrode, because the diameterof the plug electrode is smaller than the diameter of the opening, theshort margin between the storage electrode and the data line furtherincreases.

[0086] Further, because the plug electrode can be used not only on then-channel MISFETs but also on the p-channel MISFETs in the memory celland in the indirect peripheral circuit, the area required for indirectperipheral circuits, such as a sense amplifier, can be reduced withoutincreasing the process steps.

[0087] Further, as described above, even if the underneath plugelectrode is exposed in dry-etching the data line during dry-etching thedata line material, it is not etched. Therefore, if the line width ofthe data lines is decreased, no problem arises. Thus, the data lines andthe storage electrodes are connected, the short margin of the openingscan be increased. More specifically, with the wiring electrode 13protected by photoresist in the indirect peripheral circuit region, thewiring electrode 13 in the memory cell region is side-etched byisotropic dry etching. Accordingly, the wiring electrode 13 in thememory cell can be decreased in thickness while the wiring electrode 13in the indirect peripheral circuit region can be made thick at the sametime. Therefore, the depth of the opening for the storage electrode inthe memory cell can be made shallow, so that the manufacturing processcan be made easier. Incidentally, for dry etching the wiring electrode13, by side etching the material used, the size of the dry-etching maskitself may be reduced to less than the minimum-processing dimension.

[0088] <Embodiment 2>

[0089] This embodiment, which concerns the dynamic RAM in the firstembodiment but uses a capacitor of a different structure from that ofthe first embodiment, will be described with reference to FIGS. 11 and12.

[0090]FIG. 11 is a sectional view of the dynamic RAM according to asecond embodiment. In FIG. 11, the storage electrode 26 (lowerelectrode) of the capacitor is formed by a thick polysilicon film ofabout 500 nm in thickness. In other words, the storage electrode is madeby depositing a polysilicon film and then merely patterning it to theshape of the storage electrode. According to the second embodiment, thestorage electrode is of a structure with the storage capacitanceincreased by increasing the thickness of the polysilicon film andutilizing the vertical components of the sidewalls of the polysilicon.This capacitor offers the same effects as with the crown-shapedcapacitor in the first embodiment.

[0091] Note that the capacitor structure is the same as that in thefirst embodiment excepting that the storage electrode 26 is connectedthrough the opening of the silicon dioxide film 14 to the plug electrode11 of titanium nitride formed on the highly-doped n-type impurity region8 of the MISFET. The dielectric film 27 uses a high dielectric film,such as tantalum pentoxide like in the first embodiment.

[0092]FIG. 12 is a sectional view of a dynamic RAM different from thatin FIG. 11. In FIG. 12, the storage electrode 30 is formed by a platinumfilm about 100 nm thick. A capacitor dielectric film 31 made of a (Ba,Sr) TiO₃) about 30 nm thick is formed on the storage electrode 30. Aplug electrode 29, which passes through the silicon dioxide film 14, isformed in the silicon dioxide film 14 on the wiring electrode 13.Therefore, the storage electrode 30 is connected through the plugelectrode 29 to the plug electrode 11 and further electrically connectedto the MISFET. Thus, it is possible to use an electrode material thatcannot be deposited by a CVD method for better step coverage in formingthe storage electrode.

[0093] In the second embodiment, as with the plug electrode 11, titaniumnitride is preferably used as the material for the plug electrode 29, inwhich case, when a storage electrode of platinum is connected to the topof the plug electrode 29, no reaction occurs between those electrodes.

[0094] In the second embodiment, because a capacitor dielectric filmwith a high dielectric constant is used, a sufficient storagecapacitance can be secured even if a three-dimensional capacitor usingthe sidewalls of the storage electrode mentioned above is not formed.

[0095] Since the storage electrode is thin, the capacitor dielectricfilm 31 can be formed by sputtering, thus facilitating the manufactureof the dielectric film.

[0096] The capacitors described in the two embodiments are made bysimpler manufacturing processes than in the crown-shaped capacitor inthe first embodiment.

[0097] As is obvious from the foregoing, the present invention can beapplied regardless of the structure of the capacitor.

[0098] The capacitor dielectric films with a high dielectric constant asmentioned above need to be annealed at a high temperature of about 750°C. for crystallization. In the present invention, however, because plugelectrodes of titanium nitride are used for connection to the substratesilicon, they do not react with the silicon at the connection points.

[0099] The structure of the plug electrode 29 shown in FIG. 12 in thesecond embodiment can be applied to the crown-shaped capacitors in thefirst embodiment and to capacitors in other embodiments.

[0100] <Embodiment 3>

[0101] A third embodiment relates to the dynamic RAM in the firstembodiment and more particularly to the connection method of the storageelectrode. FIG. 13 is a sectional view of the dynamic RAM in the thirdembodiment and shows a method of reducing the diameter of the openingsof the silicon dioxide film 14 when connecting the capacitor storageelectrode 15 to the plug electrode 11. In FIG. 13, the structure isidentical with that in FIG. 1 excepting for the openings of the silicondioxide film 14. Plug electrodes of titanium nitride are provided on thehighly-doped n-type impurity regions of the MISFETs formed on a siliconsubstrate, and crown-shaped capacitors are formed through theintermediary of the silicon dioxide film 14 over the data line. Theopenings formed in the silicon dioxide film 14 are decreased in diameterby spacer insulators 33 along the sidewalls of the openings. Thecapacitor storage electrodes 16 are connected to the plug electrodes 11through the openings narrowed as described.

[0102] The manufacturing process of the third embodiment will bedescribed with reference to FIGS. 14 to 17.

[0103] As shown in FIG. 14, the process until MISFETs and data lines areformed on the silicon substrate is the same as in FIG. 7 showing thefirst embodiment. Subsequently, a silicon dioxide film 14 is depositedon the wiring electrode 13, and openings about 0.2 μm in diameter areformed in the silicon dioxide film 14 by photolithography and dryetching. The 0.2 μm is the minimum processing dimension inphotolithography.

[0104] After this, as shown in FIG. 16, a silicon nitride film about 50nm thick is deposited by a LPCVD method, and a silicon nitride film isformed on the sidewalls of the openings with better covering properties.A spacer insulator 33 is formed on the sidewalls of the openings of thesilicon dioxide film 14 by etch-back of the flat portion of thedeposited silicon nitride by anisotropic dry etching. After the spacerinsulators 33 have been formed, the underneath silicon nitride film 12may be etched away by overetch to form openings to the plug electrodes11. By the above-mentioned process, the openings of the silicon dioxidefilm 14 becomes about 0.1 μm in diameter.

[0105] After this, as shown in FIG. 17, a polysilicon film for storageelectrode is deposited, the crown-shaped storage electrodes 15 areformed as in the first embodiment, and a capacitor dielectric film 16and a plate electrode 17 are formed.

[0106] According to the third embodiment, in the silicon dioxide film 14on the wiring electrode 13 as the data line, the openings are formedwith a diameter less than the minimum processing dimension, so that thespace between the data line and the opening can be reduced and the shortmargin between the storage electrode and the data line can be increased.According to the third embodiment, description has been made by takingthe crown-shaped capacitor as an example, but this embodiment can beapplied to the capacitor structure in the second embodiment and otherwell-known capacitor structures.

[0107] <Embodiment 4>

[0108] A fourth embodiment of the present invention relates to thedynamic RAM in the first embodiment and also to a method of reducing theline width of the data line. FIG. 18 is a sectional view of the dynamicRAM according to the fourth embodiment.

[0109] In FIG. 18, a wiring electrode 37 as the data line is embedded atthe opening formed in the silicon dioxide film 35. A spacer insulator 36formed by a silicon nitride film is formed at this opening, and the linewidth of the wiring electrode 37 is determined by the spacer insulator36. Crown-shaped capacitor storage electrodes 15 are formed over thewiring electrode 37 and on the silicon dioxide film 38 on the silicondioxide film 35. The storage electrode 15 is connected to the plugelectrode 11 through a common opening running through the silicondioxide films 38, 35 and the silicon nitride film 12.

[0110] The fourth embodiment will be described with reference tosectional views of the manufacturing process shown in FIGS. 19 to 24.

[0111] As shown in FIG. 19, the manufacturing process until the MISFETsand the plug electrodes 11 are formed on the silicon substrate is thesame as in FIG. 6 showing the first embodiment. Further, a siliconnitride film 12 is deposited to a thickness of about 50 nm by a LPCVDmethod.

[0112] After this, as shown in FIG. 20, a silicon dioxide film 35 about200 nm in thickness is deposited by CVD using a TEOS gas, openings areformed in the silicon dioxide film 35 according to a pattern of thewiring electrode, and a silicon nitride film 41 about 50 nm thick isdeposited with better covering properties by a LPCVD method. Note that asilicon dioxide film may be used instead of the silicon nitride film.

[0113] Subsequently, as shown in FIG. 21, the silicon nitride films 41and 12 are etched by anisotropic dry etching, a spacer insulators 36 areformed on the sidewalls of the silicon dioxide film 35, and at the sametime the plug electrode 11 is exposed.

[0114] Next, as shown in FIG. 22, a tungsten film about 300 nm thick isdeposited. A CVD method is preferred as the deposition method. Afterthis, the tungsten film on the silicon dioxide film 35 is polished by aCMP method to leave the tungsten embedded only in the openings of thesilicon dioxide film 35. In this step, it is made sure that the tungstenfilm is polished about 50 to 100 nm in excess.

[0115] Subsequently, as shown in FIG. 23, a silicon dioxide film 38 isdeposited to a thickness of 100 nm, and common openings 42 are formed torun through the silicon dioxide films 38, 35 and the silicon nitridefilm 12. Incidentally, better effects can be achieved if the openingsare formed in combination with the third embodiment.

[0116] After this, as shown in FIG. 24, a polysilicon used as thestorage electrodes 15 is deposited and crown-shaped capacitors areformed as in the first embodiment.

[0117] According to the fourth embodiment, because the line width of thewiring electrode 37 as the data line can be reduced to less than theminimum-processing dimension, the short margin between the wiringelectrode 37 and the openings for connection to the storage electrodes15 can be increased.

[0118] In the fourth embodiment, description has been made by taking thecrown-shaped capacitor as an example, but this embodiment can be appliedto the capacitor structure described in the second embodiment and otherwell-known capacitor structures.

[0119] This embodiment can be applied to memory cells that do not useplug electrodes on the silicon substrate as depicted in FIG. 25 and alsoto memory cells that use polysilicon plugs.

[0120] Further, the fourth embodiment can be used not only to thedynamic RAM but also to wiring used in LSI circuits. In this case, asthe material for the wiring electrode 37, a low resistivity metal suchas aluminum or copper can be used in addition to high refractory metalwith heat resistance.

[0121] <Embodiment 5>

[0122] A fifth embodiment of the present invention relates to a memorycell of dynamic RAM type, which uses platinum for the capacitanceelectrode of the capacitor, and more particularly relates to micro-scaleprocessing of a platinum electrode. FIG. 26 shows the manufacturingprocess of a dynamic RAM according to the fifth embodiment, in whichplatinum is used for the capacitance electrode of the capacitor in orderthat a BST film of high dielectric constant or a PZT film offerro-dielectric is used for the capacitor of a memory cell.

[0123] As shown in FIG. 26, MISFETs are formed on the silicon substrate.The manufacturing process until the plug electrodes 11 and the wiringelectrodes 13 are formed is the same as the process up to FIG. 7 in thefirst embodiment.

[0124] After this, as shown in FIG. 27, a silicon dioxide film 14 about0.5 to 1 μm is deposited at a temperature of about 400° C. by awell-known CVD method using a TEOS gas, and the surface is flattened bya well-known CMP method. Further, when openings are formed in thesilicon dioxide film 14 and the silicon nitride film 12 byphotolithography and dry etching, and a titanium nitride film about 200nm thick is deposited by a CVD method. After this, the plug electrodes29 are formed by etch-back of the deposited titanium nitride film at theflat portion by anisotropic dry etching.

[0125] Subsequently, as shown in FIG. 28, a platinum film 45 with athickness of 100 to 300 nm is deposited by sputtering, and an amorphoussilicon film 43 is deposited to a thickness of about 100 nm. Theamorphous silicon film 43 is patterned by photolithography and dryetching.

[0126] Next, as shown in FIG. 29, the multilayered body thus produced isannealed to let the amorphous silicon film 43 and the platinum film 30react each other to form platinum silicide 44 at the patterned portions.That portion of the platinum film 30 where there was no amorphoussilicon film remains as is.

[0127] After this, as shown in FIG. 30, the platinum silicide 44 isremoved by wet etching using a hydrofluoric acid solution, and thusplatinum electrodes 30 are formed. It is advisable to provide a stopperto wet etching beneath the platinum films 30, though this step isomitted here.

[0128] Further, as shown in FIG. 30, a BST film 30 is deposited on theplatinum film 30 by sputtering or CVD, and a platinum film 32 isdeposited additionally, which is patterned by photolithography and dryetching. The subsequent process may be the same as in the firstembodiment.

[0129] According to the fifth embodiment, the platinum electrodes can bepatterned in a fine geometry without directly etching the platinum film.Therefore, it is possible miniaturize a capacitor which uses theplatinum film as the storage electrode.

[0130] <Embodiment 6>

[0131] A sixth embodiment of the present invention relates a static RAMto which the present invention is applied. FIG. 32 shows an equivalentcircuit of the memory cell of a static RAM. The memory cell comprises aflip-flop circuit having a pair of inverters, which include n-channelMISFETs (Q1, Q2) and p-channel MISFETs (Q5, Q6), arranged in crossconnection, and transfer transistors (Q3, Q4) connected to theflip-flop. FIGS. 33 and 34 are plan views each showing a static RAM of astructure suitable for high element integration, which has p-channelMISFETs formed in polysilicon layers. FIG. 33 shows the MISFET portionsformed on the silicon substrate, while FIG. 34 shows the TFT (Thin FilmTransistor) portions and the wiring electrode portions formed in thepolysilicon film.

[0132] In FIG. 33, the gate electrodes of the driver MISFETs areconnected to storage nodes formed by highly-doped n-type impurityregions 106, 107 as the respective drains through plug electrodes 117 oftitanium nitride formed in the openings. Further, plug electrodes 117 oftitanium nitride in the openings of the highly-doped n-type impurityregions 108, 109 as the sources of the driver MISFETs are connected tothe ground lines 116. Further, the highly-doped n-type impurity regions106, 107 at the storage nodes also serve as highly-doped impurityregions of the transfer MISFETs Q3, Q4, and the gate electrodes 110, 111of the transfer MISFETs serve as word lines common to adjacent memorycells. Plug electrodes 117 are formed in the openings of thehighly-doped n-type impurity regions 104, 105 of the transfer MISFETs,and the plug electrodes 117 are connected to the wiring electrodes129,130 (FIG. 34) as the data lines.

[0133] In FIG. 34, plug electrodes 117 formed in the storage nodes areconnected through openings 140, 1.41 to the gate electrodes 119, 120 ofthe p-channel TFTs (Q6, Q5) as the load elements. Further, the gateelectrodes 119, 120 are connected through openings 121, 122 to the drainregions 114, 115 of the other TFTs. The source regions 125, 126 of theTFTs (Q5, Q6) are the common power supply wirings for the adjacentmemory cells.

[0134] Referring to FIG. 35, the sixth embodiment will be described ingreater detail. FIG. 35 is a sectional view taken along the line X-X′ inthe plan views in FIGS. 33, 34.

[0135] The n-channel MISFETs of the memory cell are formed on thesurface of the silicon substrate. The plug electrodes 117 are formed onthe highly-doped n-type impurity regions 104, 106 and the gate electrode112. The wiring electrode 116 of the structure described in the fourthembodiment is formed on the silicon dioxide film 133. Tungsten ispreferred as the material for the wiring electrode 116. The wiringelectrode 116 acts as the ground line to supply a ground potential tothe source of the sources of the driver MISFETs. The gate electrodes119, 120 of TFTs, which are made of a p-type polysilicon film, areformed over the wiring electrode 116 through the intermediary of thesilicon dioxide film 137. A gate insulator 138 for the TFT is formed onthe gate electrode 120. The TFT channel region 123 made of polysilicon,a source region 125 and a drain region 114 are formed on the gateelectrode 138. The drain region 114 of one TFT is connected through anopening, formed at a part of the gate insulator 138, to the gateelectrode 119 of the other TFT, by which the cross connection of theflip-flop can be achieved. Further, this gate electrode 119 is connectedto the plug electrode 117 through an opening which is smaller than thediameter of the plug electrode 117.

[0136] According to the sixth embodiment, because a large short margincan be secured between the ground line of the memory cell and the gateelectrodes of the TFTs, the memory cell area of the static RAM can bereduced. Further, because the p-channel TFT and the n-channel MISFETformed on the silicon substrate are connected through a plug electrodemade of titanium nitride, an electrically ohmic contact can be obtained.

[0137] <Embodiment 7>

[0138] A seventh embodiment of the present invention is an applicationof the present invention to a static RAM in which an n-channel MISFETand a p-channel MISFET are all formed on a silicon substrate. FIGS. 36and 37 are plan views of static RAMs according to the seventhembodiment. FIG. 36 shows MISFETs and local wiring area and FIG. 37shows wiring electrodes.

[0139] In FIG. 36, MISFETs Q1, Q2, Q3, Q4, Q5 and Q6 correspond to theequivalent circuit in FIG. 32. A gate electrode 215 is a gate electrodefor Q1 and Q5. A gate electrode 216 is a common gate electrode for Q2and Q6. Plug electrodes 217, 218, 219 and 220 are formed on thehighly-doped n-type impurity regions 206, 207 of the n-channel MISFETsQ1, Q2, Q3 and Q4 and on the highly-doped p-type impurity regions 210,211 of the p-channel MISFETs Q5, Q6. Plug electrodes 221 and 222 areformed on the gate electrodes 215, 216. In other words, the crossconnection of the flip-flop of the memory cell is formed by the plugelectrodes 217, 218, 219, 220, 221 and 222 and local wirings 223 and 224formed by a tungsten film of about 100 nm in thickness. Those plugelectrodes are made of titanium nitride, are formed by a similar methodas in the first embodiment and the range of their height is from. 50 nmto 150 nm or so.

[0140] Metal wirings 231, 232, 233, 234 in the first layer shown in FIG.37 are installed through openings 225, 226, 227, 228, 229 and 230 in thehighly-doped n-type impurity regions 204, 205 of MISFETs Q3 and Q4, thehighly-doped n-type impurity regions 208, 209 of MISFETs Q1 and Q2 andthe highly-doped p-type impurity regions 212, 213 of MISFETs Q5, Q6. Themetal wiring 233 is ground wiring to supply ground potential to thesources of the driver MISFETs Q1 and Q2. The metal wiring 234 is powersupply wiring to supply power to the sources of driver MISFETs Q1 andQ2. Further, the data lines of the memory cell are formed by metalwirings 237, 238 of the second layer. The metal wirings 231, 232, 233,234, 237 and 238 are made of aluminum.

[0141]FIG. 38 is a sectional view of the seventh embodiment. Then-channel MISFET and the p-channel MISFET in the memory cell are formedrespectively in a p-well 244 and an n-well 245 in a silicon substrate201. In the seventh embodiment, as in the first embodiment, siliconnitride films 239, 240 are provided at the top and sidewalls of the gateelectrode of the MISFETs so that self-aligned contacts can be formed. Inthis case, when forming the plug electrodes 217 on the gate electrode216, photolithography and dry etching, different from those processesused in forming other plug electrodes, should preferably be carried out.Though not shown, if silicon nitride is used as the etching stopper forthe isolation, a structure is obtained that can be borderless.

[0142] According to the seventh embodiment, the local wiring can bemicrominiaturized, so that a static RAM with high device integration canbe provided.

[0143] <Embodiment 8>

[0144] An eighth embodiment of the present invention is an improvedversion of the static RAM in the seventh embodiment, in which the crossconnection of the flip-flop circuit can be achieved with four plugelectrodes. FIG. 39 is a plan view of the static RAM according to theeighth embodiment, in which the wiring electrode portion, beingidentical to that in the seventh embodiment, is omitted here. FIG. 40 isa sectional view. In FIGS. 39 and 40, the plug electrode 217 on thehighly-doped n-type impurity region 206 of the driver MISFET isconnected to the local wiring 221 formed by tungsten about 100 nm thick,which is above the plug electrode 217. The local wiring 221 is alsoconnected to the common gate electrode 216 of the mating inverter (Q2,Q6) and at the same time to the highly-doped p-type impurity region 210of the load MISFET Q5, by a plug electrode 246 which extends on thecommon electrode 246 and the region 210. A plug electrode 247 in FIG. 39is connected in a similar manner. The above-mentioned plug electrodesare made of titanium nitride, and formed by the same method as in thefirst embodiment.

[0145] According to the eighth embodiment, the local wiring can befurther miniaturized and a static RAM with high device integration canbe provided.

[0146] <Embodiment 9>

[0147] A ninth embodiment of the present invention relates to a memorycell of another system in the static RAM according to the presentinvention. FIGS. 41 and 42 are plan views of the memory cell of thestatic RAM according to the ninth embodiment. FIG. 41 shows MISFETs andFIG. 42 shows wiring electrodes. In FIG. 41, for the cross connection ofthe flip-flop circuit, plug electrodes 318, 319, 320, 321 and 322 areused for connections without using local wirings. Those plug electrodesare made of titanium nitride, and formed by the same method as in thefirst embodiment. The wiring electrodes are made of two layers ofaluminum as in the seventh embodiment.

[0148] According to the seventh embodiment, the manufacturing process ofthe static RAM can be simplified.

[0149] In the embodiments of the memory cell described above, both in astatic RAM and a dynamic RAM, the indirect peripheral circuit uses plugelectrodes of a common self-aligned structure explained in the firstembodiment, so that the required area of the indirect peripheral circuitcan be reduced.

[0150] In the embodiments described above, the present invention isapplied to those semiconductor devices in which a static RAM and adynamic RAM coexist on the same silicon substrate or other semiconductordevices in which memory devices and logic circuits exist side-by-side.Therefore, production cost can be reduced, data transfer rate can beincreased, and chip area can be decreased.

[0151] As has been described, according to the present invention, itbecomes possible to reduce the required area for CMISFETs not only inthe memory cells but also in the indirect peripheral circuits. In amemory cell of a multilayered structure in which a device is formedabove a MISFET, when the memory cell undergoes a hot working processnecessary for its formation, the electrical characteristics of theconnections between the plug electrodes and the silicon substrate arenot impaired. Thus, the memory cells are provided with stablecharacteristics.

[0152] Further, the short margin between the element located at a higherposition and a wiring layer at a middle position of the MISFET can beincreased. Therefore, it becomes possible to provide a semiconductordevice with a smaller chip area.

[0153] According to the present invention, it is possible to provide asemiconductor memory device capable of much higher-speed operations bythe use of a low resistivity metal, such as copper, for the wiring layerabove the capacitor in the memory cell region and for the wiring layerin the indirect peripheral circuit region.

Industrial Applicability

[0154] In the embodiments described above, the present invention hasbeen applied to the dynamic RAM and the static RAM.

[0155] However, the present invention can be applied to semiconductorintegrated circuit devices, such as an on-chip LSI in which memory andlogic (logic circuits) exist commingled. In this case, a wiring layer ofthe logic portion can be formed at a height where there is a capacitor.The logic portion comprises a plurality of CMISFETs. In other words, thelogic portion is formed by COS logic.

1. A semiconductor memory device comprising: a memory cell region,including a first transistor provided on a principal surface of asemiconductor substrate; and a logic circuit region, including secondand third transistors of mutually different conductivity types, whereinon a principal surface of a first insulating film above said first,second and third transistors, a first wiring made of a first metal isformed in a memory cell region and a logic circuit region, and whereinsaid first wiring is connected to said first, second and thirdtransistors through a connecting body, including first conductorsprovided in openings passing through said first insulating film.
 2. Asemiconductor memory device according to claim 1, wherein saidsemiconductor substrate is made of silicon, and wherein the propertiesof said first conductor and first metal are such that said firstconductor does not increase contact resistance by reaction with saidsilicon and that said first conductor is lower in etching rate than thefirst metal.
 3. A semiconductor memory device according to claims 1 and2, wherein said first conductor and said first metal are mutuallydifferent high refractory metals.
 4. A semiconductor memory deviceaccording to claims 1 to 3, wherein said first conductor is titaniumnitride or titanium-tungsten, and wherein said first metal is tungsten.5. A semiconductor memory device according to claim 1, wherein saidfirst conductor is connected through a silicide layer to said siliconsubstrate.
 6. A semiconductor memory device according to claim 1,wherein a source region, a drain region and a gate electrode of each ofsaid first, second and third transistors are connected through aconnecting body including said first conductor to said first metal.
 7. Asemiconductor memory device having a memory cell, including a firsttransistor on a principal surface of a silicon substrate and a firstwiring formed by a first metal, said first wiring being laid through afirst insulating film and a second insulating film above said firsttransistor, wherein a first element is formed on said first wiringthrough a third insulating film, and wherein said first element isconnected to said first transistor through a connecting body including afirst conductor provided in an opening passing through said firstinsulating film, and a second conductor provided in an opening passingthrough said second insulating film and a third insulating film.
 8. Asemiconductor memory device according to claim 7, wherein said firstconductor and said second conductor are substantially cylindrical, andwherein said first conductor is electrically insulated from said gateelectrode by fourth and fifth insulating films formed at sidewalls and atop of said gate electrode of said first transistor, wherein a part ofsaid first conductor is so arranged as to overlie said gate electrode ofsaid first transistor and a sixth insulating film for isolation, andwherein an average diameter of said second conductor is smaller than anaverage diameter of said first conductor.
 9. A semiconductor memorydevice according to claim 1, wherein a width of said first wiring issmaller than an average diameter of said first conductor at the openingpassing through said first insulating film.
 10. A semiconductor memorydevice according to claim 1 or 7, wherein said first wiring is the dataline of a dynamic random access memory cell, and wherein said firstelement is a capacitor of a dynamic random access memory cell.
 11. Asemiconductor memory device according to claim 7, wherein said firstelement is a polysilicon transistor of a static random access memorycell, and wherein said first wiring is power supply wiring of saidstatic random access memory.
 12. A semiconductor device according toclaim 11, wherein said first wiring is local wiring connecting gateelectrodes or source and drain regions of transistors of mutuallydifferent conductivity types.
 13. A semiconductor device comprising amemory cell including a first transistor provided on a principal surfaceof a silicon substrate, and a logic circuit including second and thirdtransistors of mutually different conductivity types, wherein on aprincipal surface of a first insulating film, a plurality of firstwirings made of a first metal are formed in a memory cell region and alogic circuit region, wherein said first wirings are connected to saidfirst, second and third transistors by connecting body including saidfirst wiring and passing through said first insulating film, wherein asecond insulting film is provided on said first wiring, wherein a firstelement is provided on a principal surface of said second insulatingfilm in the memory cell region, and wherein said first element isconnected to said first transistor by a connecting body including saidfirst conductor and second conductor penetrating into said secondinsulating film.
 14. A semiconductor device according to claim 13,wherein said second conductor is formed of titanium nitride.
 15. Asemiconductor memory device according to claim 1, further comprising apair of inverters, each including said second and third transistors; alatch-type flip-flop circuit formed by said pair of inverters; a pair ofsignal lines connected to said flip-flop circuit; and first and secondswitching transistors formed by said second or third transistors,wherein a connecting body having the gate of each of said pair ofinverters connected to the drain of the other inverter in crossconnection includes said first wiring and said first conductors.
 16. Asemiconductor integrated circuit device having a first insulating filmprovided on a principal surface of a semiconductor substrate and a firstwiring formed by a conductor filled in a first opening in said firstinsulating film, wherein insulating side walls formed of otherinsulating films are deposited on side walls of said first opening ofsaid first insulating film and a line width of said first wiring isdefined by said side walls.
 17. A semiconductor integrated deviceaccording to claim 16, wherein said first wiring is formed by a highrefractory metal.
 18. A semiconductor integrated device according toclaim 16, wherein said first wiring has a sectional contour of aninverted taper.
 19. A semiconductor integrated device according to claim16, wherein said fourth insulating film is silicon nitride.
 20. Asemiconductor integrated circuit device according to claim 16, whereinon said semiconductor substrate, there are formed a latch-type flop-flopcircuit formed by a pair of inverters connected to a pair of signallines; first and second switching transistors connected to respectivesignal lines; first power supply wiring; second power supply wiring; andcontrol lines connected to said first and second switching transistors,either of said first and second power supply wirings and either of saidfirst and second control lines include at least said first wiring.
 21. Asemiconductor integrated circuit device according to claim 16, whereinon a principal surface of said semiconductor substrate, there is formeda dynamic random access memory, including a memory cell formed by aswitching transistor and an electric charge storage capacitor connectedto said switching transistor; a word line for selecting said switchingtransistor; and a data line for reading and writing information, whereinsaid data line is formed by said first wiring.
 22. A method formanufacturing a semiconductor integrated circuit device, comprising thesteps of: forming a MISFET on a semiconductor substrate; depositing afirst insulating film; etching a desired region in said first insulatingfilm and forming a first opening for a wiring pattern; depositing asixth insulating film and forming sidewall spacers formed by saidseventh insulating film at sidewalls of said first opening byanisotropic etching; and depositing a first conductor in said firstopening.
 23. A method of manufacturing a semiconductor integratedcircuit device, comprising the steps of: forming a MISFET on a MISFET ona semiconductor substrate; depositing a first insulating film on saidMISFET; depositing a platinum film on said first insulating film;depositing amorphous silicon on said platinum film and dry etching theamorphous silicon at a desired region; forming platinum silicide at thatregion on said platinum film where there is amorphous silicon, by heattreatment; and removing said platinum silicide by wet etching to thereyleave a platinum electrode intact at a desired region.
 24. A method ofmanufacturing a semiconductor integrated circuit device according toclaim 23, wherein said platinum electrode is an electrode of a capacitorof a dynamic random access memory cell, said capacitor electrode beingformed raised on the principal surface of the semiconductor substrate.